Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-12-19
2002-05-14
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330, C365S185220
Reexamination Certificate
active
06388919
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a memory controller for a flash memory system, a flash memory system and a method for writing data to a flash memory device, and particularly, to such a memory controller and a flash memory system that can write data to a flash memory device accurately and a method for writing data to a flash memory device accurately.
DESCRIPTION OF THE PRIOR ART
In recent years, flash memory devices, particularly NAND type flash memory devices, are widely used as semiconductor memory devices for memory cards, silicon disks and the like. In such a NAND type flash memory device, although a transition from an erased state (logical value=“1”) to a programmed state (logical value=“0”) can be performed for each memory cell as an individual unit, a transition from the programmed state (0) to the erased state (1) cannot be performed for each memory cell as an individual unit. Such a transition from the programmed state (0) to the erased state (1) can be only performed for a predetermined number of memory cells as a unit, called a “block”, constituted of a plurality of memory cells. Such an operation is called “block erasing”.
According to the NAND type flash memory device, because the transition from the programmed state (0) to the erased state (1) cannot be performed for each memory cell as an individual unit, in order to write data into a certain block, it is required to perform a block erasing operation to change the states of all memory cells included in the block to the erased state (1). A block-erased block becomes a free block in which no data are stored. In order to write new data into a flash memory device, search is made for such a free block and the new data are written into a found free block.
Because the flash memory device is a type of non-volatile memory device, the states of the memory cells of the flash memory device are maintained for a very long time regardless of whether power voltage is applied. Therefore, the data stored in the memory cells and the state of a free block of the flash memory device are reliably maintained after power voltage is cut off.
However, when reading or writing is performed with respect to a certain memory cell, gradual change may occur in the state of other memory cells connected to the same bit line as the certain memory cell owing to the “disturb phenomenon”. It is known that incidence of the disturb phenomenon increases when the reading or writing operation is repeated. If the state of a memory cell is changed by the disturb phenomenon, not only are stored data corrupted but writing operation is also not successfully performed.
FIGS.
1
(
a
) to
1
(
d
) are schematic diagrams for explaining how writing operation is not successfully performed owing to the disturb phenomenon.
FIG.
1
(
a
) shows the logical values of each of the memory cells constituting a page n right after block erasing. The page n is constituted of 8 memory cells and can store 256 (2
8
) bits of data. As shown in FIG.
1
(
a
), all memory cells constituting the page n are in erased state (logical value of “1”) right after block erasing. In the case where the logical values of all memory cells constituting the page n are “1”, data stored in the page n is FFh.
FIG.
1
(
b
) shows the logical values of each of the memory cell constituting the page n in the case where the states of two memory cells thereof were changed from the erased state (1) to the programmed state (0) owing to the disturb phenomenon. Because the states of two memory cells have spontaneously changed to the programmed state (0), the data stored in the page n is changed to DDh as shown in FIG.
1
(
b
).
FIG.
1
(
c
) shows logical values of data (AAh) to be written in page n and the logical values of each of the memory cells constituting page n. To write the data (AAh) to page n, such an operation is performed that change the states of the memory cells corresponding to the bits whose logical value is “0” in the write data (AAh) from the erased state to the programmed state. No operation is performed on the memory cells corresponding to the bits whose logical value is “1” in the write data (AAh). Note that the data stored in page n was changed form FFh to DDh owing to the disturb phenomenon before writing of the data (AAh) thereto.
FIG.
1
(
d
) shows the logical values of each of the memory cell constituting page n after the data (AAh) have been written. Because the writing operation is performed such that, on the one hand, the states of the memory cells corresponding to the bits whose logical value is “0” in the write data (AAh) are changed from the erased state to the programmed state and, on the other hand, the states of the memory cells corresponding to the bits whose logical value is “1” in the write data (AAh) are not changed, as mentioned above, the states of the two memory cells whose states were changed by the disturb phenomenon are maintained in the programmed state. As a result, the data stored in page n is not AAh but 88h. That is, incorrect data is stored.
As is apparent from the foregoing, the writing operation is not successfully performed if the states of the memory cells are changed owing to the disturb phenomenon.
If the power voltage is suddenly cut off during block erasing, it is possible that the memory cells in the block may not be sufficiently erased. Although this is not caused by the disturb phenomenon, in this case too, the writing operation is not successfully performed for the same reason as explained above.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a memory controller which can write data correctly to flash memory devices.
Another object of the present invention is to provide a flash memory system which employs a memory controller which can write data correctly to flash memory devices.
A further object of the present invention is to provide a method for writing data correctly to flash memory devices.
The above and other objects of the present invention can be accomplished by a memory controller for accessing a flash memory device, comprising: search means for finding an erased block in said flash memory device in response to a data writing request from a host computer, verify means for verifying a state of said erased block found by said search means, and store means for storing data into said erased block which has been verified by said verify means.
According to this aspect of the present invention, improper data cannot be stored so that the quality of the data writing can be improved because verification of the state of the erased block in which data are to be stored is performed prior to data writing thereto.
In a preferred aspect of the present invention, the verify means verifies whether or not all flash memory cells constituting the erased block found by the search means are in an erased state.
In a further preferred aspect of the present invention, the memory controller further comprises test means, responsive to detection by said verify means of flash memory cell in a different state from said erased state, for testing whether or not said erased block is a defective block with a permanent error.
According to this preferred aspect of the present invention, in the case where a flash memory cell whose state is different from the erased state is detected, it is judged whether the block should be excluded. Therefore, exclusion of a defective block having a transient error can be avoided.
In a further preferred aspect of the present invention, the test means performs writing and first reading operations to store and read first test data to/from all flash memory cells constituting said erased block.
In a further preferred aspect of the present invention, the test means further performs erasing and second reading operations to store and read second test data to/from all flash memory cells constituting said erased block.
The above and other objects of the present invention can be also accomplished by a flash memory system, comprising: at least one flash memory chip divided
Brown & Raysman Millstein Felder & Steiner LLP
Hoang Huan
TDK Corporation
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