Memory controller for both interleaved and non-interleaved memor

Details Memory controller for both interleaved and non-interleaved memor Memory controller for both interleaved and non-interleaved memor

1995-06-06

1997-04-08

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36523004, G11C 800

Patent

active

056194714

ABSTRACT:
A system and method for controlling DRAM is described. According to exemplary embodiments of the present invention, a memory subsystem can be populated by end users with any of a variety of DRAM chips. A memory controller will size each memory bank and determine whether paired memory banks are to be configured as interleaved or non-interleaved based upon the detected DRAM population. Bank selection logic is designed to account for both size and status (interleaved or non-interleaved) when determining which memory bank contains a memory location of interest. Row and column addressing is selected to minimize decoding of an incoming system address and reduce DRAM access time.

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AM29200.TM. Risc Microcontroller User's Manual and Data Sheet, pp. 9-1 thru 9-10 (Chapter 9, DRAM Controller) Nov. 1991.

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