Memory controller and method of aligning write data to a...

Details Memory controller and method of aligning write data to a... Memory controller and method of aligning write data to a...

2005-07-12

2005-07-12

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000

Reexamination Certificate

active

06917561

ABSTRACT:
A memory controller for aligning write data and a clock strobe signal provided to a memory device includes a delay line coupled to a local clock input and providing as an output a delayed local clock signal. A first latch circuit receives data to be written to the memory device as an input and has an output coupled to a data input of the memory device. The first latch circuit is clocked by a first one of the local clock signal and the delayed local clock signal and provides in response the write data to the data input of the memory device. A clock strobe generating circuit is clocked by a second one of the local clock signal and the delayed local clock signal. The clock strobe generating circuit has an output coupled to a clock strobe input of the memory device and provides the clock strobe signal to the memory device.

REFERENCES:
patent: 5764591 (1998-06-01), Matsui et al.
patent: 6370067 (2002-04-01), Ko et al.
patent: 6839301 (2005-01-01), Lin et al.

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