Memory controller and memory system

Details Memory controller and memory system Memory controller and memory system

2007-02-13

2007-02-13

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000

Reexamination Certificate

active

11211861

ABSTRACT:
A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.

REFERENCES:
patent: 6078546 (2000-06-01), Lee
patent: 6477110 (2002-11-01), Yoo et al.
patent: 6600681 (2003-07-01), Korger et al.
patent: 6603706 (2003-08-01), Nystuen et al.
patent: 6785189 (2004-08-01), Jacobs et al.
patent: 7032092 (2006-04-01), Lai

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