Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1998-11-03
2001-11-20
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C345S098000
Reexamination Certificate
active
06320575
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory controller for storing image data of one frame from a personal computer or the like in a memory and then reading the data out of the memory for subsequent use, as well as a liquid crystal display using the memory controller.
2. Description of the Related Art
Hitherto, when storing image data of one frame from a personal computer or the like in a memory, a memory controller constructed as shown in
FIG. 5
has been used. In the memory controller shown in
FIG. 5
, reference numeral
3
denotes a counter for generating a memory address. The counter
3
increments the count value upon receiving an enable signal
10
, resets the count value upon receiving a reset signal and increments the clock count upon receiving a clock signal
8
. Reference numeral
4
denotes a vertical synch signal detecting block which receives a vertical synch signal
7
for detection of the vertical synch signal, and outputs the reset signal to the counter
3
. Reference numeral
6
denotes a frame memory for storing an image signal (not shown) of
1
frame in accordance with the address generated by the counter
3
.
Specifically, it has been customary that the address of the memory
6
is generated by incrementing the counter
3
during the effective period of the enable signal
10
, which corresponds to the effective period of an input image. Also, the reset signal for the counter
3
is generated upon the vertical synch signal detecting block
4
detecting an edge of the vertical synch signal
7
, which is in synch with each frame.
A timing chart for explaining the operation of the memory controller is shown in FIG.
6
. Referring to
FIG. 6
, when a signal XENBL indicating the effective period of image data DATA transitions to a low level, the counter
3
is incremented in synch with the clock signal CLK, which is in turn in synch with the input image. When the signal XENBL transitions to a high level upon reaching the end of data of one line, the counter
3
stops incrementing. Then, when the signal XENBL transitions to a low level again upon the start of image data of next line, the counter
3
once again increments from the point at which counting was stopped. When data of
1
frame is completed, a vertical synch signal VD is input. A signal “xvdrst” is generated from the vertical synch signal VD and a signal vd_s, generated by passing the signal VD through one step of a F/F (Flip/Flop). The memory address is reset only by the signal “xvdrst”.
In a memory controller thus constructed, however, if the address generating counter is incremented too much or too little due to an error caused by, e.g., a temporary malfunction of the clock signal, which is supposed to be in synch with the input image, the correct address can no longer be generated until the appearance of the next vertical synch signal after the occurrence of the error. This results in a problem that the image data cannot be correctly written in the memory. This also raises another problem that when reading the image data out of the memory, the image data cannot be read correctly after the occurrence of an error. For example, as shown in
FIG. 6
, an abnormal condition may occur such that the clock signal CLK enters the counter in an excessive number and that the counter is thereby incremented too much. In such an event, the generated addresses are all out of order after the occurrence of the abnormal condition, and when reading the image data, the data is read out of order.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory controller comprising a first counter and a second counter, each having reset and enable functions, a vertical synch signal detector and a horizontal synch signal detector, wherein a reset signal for the first counter is controlled by a signal detected by the vertical synch signal detector, an enable signal for the first counter and a reset signal for the second counter are controlled by a signal detected by the horizontal synch signal detector, an enable signal for the second counter is controlled in accordance with a signal indicating an image effective period, and a memory address is controlled by the first and second counters.
The present invention includes a memory controller in which the image effective period comprises pixels in number 2
n
(where n is a positive integer), and the number of bits of the second counter is n. The present invention further includes a memory controller in which the signal indicating the image effective period is generated inside of the memory controller on the basis of the horizontal synch signal and applied to the second counter as the enable signal. A liquid crystal display of the present invention advantageously may include any of the memory controllers set forth above.
With the present invention, an error-resistant memory controller can be constructed in which even if correct addresses cannot be produced for a memory due to an error caused by, e.g., a temporary malfunction of a clock signal which is to be input in synch with an image, it is possible to restore the addresses to correct values from a next line because the second counter is reset by the horizontal synch signal.
REFERENCES:
patent: 5548332 (1996-08-01), Topper et al.
patent: 5870141 (1999-02-01), Matsumura et al.
Sakashita Yukihiko
Terashima Yoshihiro
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Wu Xiao
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