Static information storage and retrieval – Addressing – Sequential
Reexamination Certificate
1996-07-11
2004-06-15
Robertson, David L. (Department: 2186)
Static information storage and retrieval
Addressing
Sequential
C711S218000
Reexamination Certificate
active
06751160
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a memory control apparatus which can effect access to a memory from a CPU or the like at a high speed.
2. Related Background Art
Hitherto, in such a memory control apparatus, address information which is outputted from a processor such as a CPU or the like is supplied as is to a memory, and a memory access is performed. To raise memory accessing speed, means for dividing the memory into two blocks in advance and alternately accessing one or the other of them, or means for dividing the memory into more than two blocks and sequentially accessing each has been used.
However, according to the method of directly supplying the address that is outputted from the CPU or the like to the memory, propagation delay of the address signal to the memory, access time of the memory, propagation delay of the data to the CPU, and the like, are added, so that the accessing speed decreases. According to the method of dividing the memory into two or more blocks, an address and a data bus are needed for every memory block, and so the circuit is complicated, and the circuit scale enlarges.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, there is provided a memory control apparatus for performing a burst access, comprising: counter means which can load each word in a burst cycle to a memory address line which is selected; and data holding means for temporarily holding data read out from a memory, wherein the first address of the burst access in a memory reading cycle that is generated by an apparatus for reading out data from the memory is loaded into the counter means, and before a timing to read the data in each reading cycle of the burst access, the data read out from the memory is held into the data holding means by using the address from the counter means, the counter means is counted up, and the address is progressed to a next address.
REFERENCES:
patent: 5319759 (1994-06-01), Chan
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5550784 (1996-08-01), Takai
patent: 5603041 (1997-02-01), Carpenter et al.
patent: 5657287 (1997-08-01), McLaury et al.
patent: 5659515 (1997-08-01), Matsuo et al.
Graphic Symbols for Logic Function-IEEE Std 91a-1991 and IEEE Std 91-1984; 1991; pp. S-34 & 81.
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