Memory control unit with selective execution of queued read and

Details Memory control unit with selective execution of queued read and Memory control unit with selective execution of queued read and

1990-09-06

1995-01-03

Black, Thomas G.

Boots, shoes, and leggings

395425, 395725, 3642395, 36424291, 3642466, 364DIG1, 36493701, 3649391, 364969, 364DIG2, G06F 1316

Patent

active

053793790

ABSTRACT:
A memory control unit (MCU) 22 includes a first interface for interfacing the memory control unit to one or more memory units; a second interface for interfacing the memory control unit to a system bus, including a system data bus for expressing information units, including memory read and write requests, and a system address bus. The MCU further includes logic, responsive to a write request from the system bus, for storing one or more information units within a memory unit at an address specified by the system address bus. The storing logic includes write request receiving and buffer logic having a plurality of storage locations for storing received write requests and associated write addresses prior to the execution of the write requests. The MCU further includes logic, responsive to a read request from the system bus, for reading one or more information units from a memory unit at a location specified by the system address bus. The reading logic includes read request receiving and buffer logic having a plurality of storage locations for storing received read requests and associated read addresses prior to the execution of the read requests. The memory control unit further has logic for comparing a received read address to write addresses stored in the write address buffer, the comparing logic having an output for indicating, when asserted, the occurence of the reception of a read address having a value within a predetermined range of values of one of the stored write addresses.

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