Memory control system

Details Memory control system Memory control system

1987-05-04

1989-12-19

Chan, Eddie P.

Boots, shoes, and leggings

3642544, 3642549, G06F 1206, G06F 1300

Patent

active

048886874

ABSTRACT:
A system for controlling the addressing of a memory on a predetermined multi-megabyte decode boundary. An address shifter is coupled between CPU address lines and backplane area bussed address lines. The address shifter is controlled in accordance with the control signal determined by the memory array of largest capacity of all memory arrays. The control signal has different states to control the address shifter to couple different address bit patterns therethrough to the backplane area address bus as a function of the selected control signal state.

REFERENCES:
patent: 4234934 (1980-11-01), Thorsrud
patent: 4545010 (1985-10-01), Salas et al.
patent: 4654787 (1987-03-01), Finnell et al.
patent: 4675808 (1987-06-01), Grinn et al.
patent: 4682283 (1987-07-01), Robb
patent: 4740916 (1988-04-01), Martin
patent: 4760522 (1988-07-01), Weatherford et al.

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