Memory control system

Details Memory control system Memory control system

1979-03-13

1982-02-02

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 906

Patent

active

043143326

ABSTRACT:
Disclosed is a memory control system for a data processing system in which the length of an access unit to a memory can be different from the lengths of information words which can be processed and which can include data, addresses, and instructions and operands processed in an arithmetic control apparatus, and combinations thereof. The disclosed memory control system provides an address boundary for effecting a read/write operation with respect to the memory of information words having a half-word length and a full-word length. The half-word length information words can correspond to 2n times a minimum word length, n being a positive integer, and the access unit length can be equal to the minimum unit word length. In a disclosed embodiment, the minimum unit word length and the access unit length can be an 8 bit byte. Thus, a half-word length can be 16 bits and a full-word length can be 32 bits.

REFERENCES:
patent: 3778776 (1973-12-01), Hakozaki
patent: 3953835 (1976-04-01), Cuccio et al.
patent: 3955180 (1976-05-01), Hirtle
patent: 4087854 (1978-05-01), Kinoshita et al.
patent: 4122531 (1978-10-01), Tamaru et al.
Flores, I., Computer Organization, 1969, pp. 252-257.

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