Memory control device with vector processors and a scalar proces

Details Memory control device with vector processors and a scalar proces Memory control device with vector processors and a scalar proces

1992-04-06

1995-12-12

Kriess, Kevin A.

Boots, shoes, and leggings

364DIG1, 36423221, 364239, G06F 1516

Patent

active

054758491

ABSTRACT:
A memory control unit connected to a scalar processor having a buffer for storing a copy of block data of a main storage and a vector processor having a store requester for writing data into the main storage is disclosed. The memory control unit has a block valid memory having a one-bit valid bit for all blocks. The valid bit represents that the copy of the block data corresponding to said bit is in the buffer of the scalar processor. The memory control unit further has a block group valid table which has a block group bit for each block group. The block group bit represents whether any one of the block valid bits of the block belonging to the corresponding group is valid or not. When the vector processor stores the data into the main storage by the store requester, the memory control unit first searches the block group valid table to check whether the block group valid bit of the block group including the store address is valid or not. If it is valid, the memory control unit further searches the block valid memory to check whether the block valid bit of the block including the store address is valid or not. If it is valid, it invalidates the buffer of the scalar processor.

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Censier, Lucien M., et al. "A New Solution to Coherence Problems in Multicache Systems," IEEE Transactions on Computers, vol. C-27, No. 12, Dec. 1978, pp. 1112-1118. (provided in English).

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