Memory control device and method operated in consecutive access

Details Memory control device and method operated in consecutive access Memory control device and method operated in consecutive access

1995-02-28

1997-04-08

Asta, Frank J.

Boots, shoes, and leggings

395484, 395854, 395873, 395881, 395551, 364DIG1, G06F 1200

Patent

active

056196792

ABSTRACT:
A memory control device and method receives a request to transfer a series of first-unit K byte (for example, 512) data in an address space, divides the first-unit K into second-unit L (for example, 64), assigns priority levels to the second-unit L, issues plural times a data transfer instruction to transfer the L-byte data to a memory device comprising a plurality of memories operable in a consecutive access mode, and thus accesses memories in response to the request to transfer the K-byte data. The L-byte data are sequentially allocated in third units S (for example, 64) specified by the data transfer instruction to the memories. The third unit is equal to L or is obtained by dividing L, and is a multiple of an activation unit of the memories. The S-byte data are accessed in the allocated memories in the consecutive access mode.

REFERENCES:
patent: 4422160 (1983-12-01), Watanabe
patent: 4429375 (1984-01-01), Kobayashi et al.
patent: 4485461 (1984-11-01), Kobayashi
patent: 5051889 (1991-09-01), Fung et al.
patent: 5163132 (1992-11-01), DuLac et al.

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