Memory control device and memory control method

Details Memory control device and memory control method Memory control device and memory control method

2006-05-09

2006-05-09

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S222000, C365S203000

Reexamination Certificate

active

07042798

ABSTRACT:
It is intended to provide a memory control device and memory control method capable of reducing charge/discharge current consumed while various commands are inputted to a semiconductor memory device and reducing occurrence of power noises. During periods TT1, TT2, and TT3which are parts of a period tCKE in which a clock enable signal CKE is in active state, supply of a control clock SD_CLK from a memory control device1to a synchronous-type semiconductor memory device12can be stopped. Furthermore, in case an input of a data input/output period of an external command and that of refresh operation period of a refresh command RCMD overlap and an access region of the external command and that of the refresh command RCMD do not coincide, those commands are converted to control command signal SD_CMD in parallel, whereby parallel conversion processing operation can be conducted.

REFERENCES:
patent: 6243320 (2001-06-01), Hamamoto et al.
patent: 6876592 (2005-04-01), Takahashi et al.
patent: 2000-029779 (2000-01-01), None

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