Memory control circuit for reducing the number of row address si

Details Memory control circuit for reducing the number of row address si Memory control circuit for reducing the number of row address si

1994-02-28

1996-06-04

Swann, Tod R.

39542101, G06F 1200

Patent

active

055242286

ABSTRACT:
A method of accessing a dynamic random access memory, including the steps of latching an upper address of the most recent address signal supplied from a requesting element, sending out the upper address of the most recent address signal and an active row address strobe signal to the dynamic random access memory, and sending out a lower address of the most recent address signal and an active column address strobe signal to the dynamic random access memory. In this method, the latched upper address is compared with an upper address of a subsequent address signal supplied from the requesting element at the time of the next access request. If the two upper addresses coincide, a lower address of the subsequent address signal and an active column address strobe signal are sent to the dynamic random access memory.

REFERENCES:
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patent: 4924375 (1990-05-01), Fung et al.
patent: 4933910 (1990-06-01), Olson et al.
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patent: 5007020 (1991-04-01), Inskeep
patent: 5051889 (1991-09-01), Fung et al.
patent: 5058005 (1991-10-01), Culley

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