Boots – shoes – and leggings
Patent
1991-01-08
1993-09-21
Dixon, Joseph L.
Boots, shoes, and leggings
364DIG1, G06F 1300
Patent
active
052476430
ABSTRACT:
A memory system for use with a copy back cache system includes a control circuit that reduces the amount of time to complete a copy back/line fill operation in which a first line of data from the cache is stored in the memory system and then a second line of data is retrieved from the memory system and transferred to the cache system. Unlike conventional memory systems where the line of data to be copied back is likely to be stored in the memory system at a row address that differs from the row address of the line of data to be retrieved from the memory system for the line fill, the memory system of the present invention assures that the copy back data and the line fill data are located at the same row address in the memory system. Thus, a single row address can be applied once at the beginning of the copy back/line fill operation, thereby saving the row address precharge time and the row address access time required to switch row addresses between the two portions of the operation.
REFERENCES:
patent: 4803621 (1989-02-01), Kelly
patent: 4894770 (1990-01-01), Ward et al.
patent: 4933835 (1990-06-01), Sachs et al.
patent: 4933837 (1990-06-01), Freidin
patent: 5022004 (1991-06-01), Kurtze et al.
patent: 5053874 (1991-08-01), Gagliardo et al.
Cliff Rhodes, "Caches keep main memories from slowing down fast CPUs,"Electronic Design, Jan. 21, 1982, pp. 179-184.
Cliff Rhodes, et al., "Cache-memory functions surface on VLSI chip," Electronic Design, Feb. 18, 1982, pp. 159-163.
Jerry VanAken, "Match cache architecture to the computer system," Electronic Design, Mar. 4, 1982, pp. 93-95, 97, 98.
Efrem G. Mallach, "What does cache buy for you?", Mini-Micro Systems, May 1982, pp. 267, 268, 271.
Robert Hartwig, et al., "Large disk cache uses fast 64k-by-1 static RAMs to speed data-base accesses," Electronic Design, Sep. 19, 1985, pp. 193-198, 200, 202.
Howard Sachs, "Improved Cache Scheme Boosts System Performance," Computer Design, Nov. 1, 1985, pp. 83-86.
Alan Jay Smith, "Cache memory design: an evolving art," IEEE Spectrum, Dec. 1987, pp. 40-44.
David Shear, "Cache-memory systems benefit from on-chip solutions," EDN, Dec. 10, 1987, 245-249, 252, 253, 258, 260.
William Ringer, "How to Manage Your Cache Options," ESD: The Electronic System Design Magazine, Jun. 1988, pp. 71, 72, 74, 75.
Jim Langston, "Boost DRAM performance with SRAM caching scheme," Electronic Design, Jun. 9, 1988, pp. 107-112.
Richard Crisp, et al., "Designing A Cache For A Fast Processor," Electronic Design, Oct. 13, 1988, pp. 111-116, 118.
Mark D. Hill, "A Case for Direct-Mapped Caches," Computer, Dec. 1988, pp. 25-40.
Mammad Safai, "Cache Design Paces 33-MHz 80386 CPUs," Microprocessor Design Guide, 1989, pp. 39, 42, 44, 46, 48.
Joseph C. Circello, et al., "Refined method brings precision to performance analysis," Computer Design, Mar. 1, 1989, pp. 77-80, 82.
Jim Peterson, "System-Level Concerns Set Performance Gains," High Performance Systems, Sep. 1989, pp. 71-73, 76, 77.
Raymond M. Leong, "Cache memories and MMUs work together in high-speed systems," EDN, Mar. 15, 1990, pp. 169-172, 174.
AST Research Inc.
Dixon Joseph L.
Elmore Reba I.
LandOfFree
Memory control circuit for optimizing copy back/line fill operat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory control circuit for optimizing copy back/line fill operat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory control circuit for optimizing copy back/line fill operat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1057037