Memory control apparatus for synchronous memory unit with...

Details Memory control apparatus for synchronous memory unit with... Memory control apparatus for synchronous memory unit with...

2007-01-16

2007-01-16

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S236000, C365S189070

Reexamination Certificate

active

11073807

ABSTRACT:
In a memory control apparatus for controlling a synchronous memory unit, the apparatus receives a source clock signal, switches ON and OFF the source clock signal in accordance with an access request signal to the synchronous memory unit and an idle state with no access request signal, and transmits the switched ON/OFF source clock signal to the synchronous memory unit, so that the switched ON/OFF source clock signal serves as an internal clock signal within the synchronous memory unit.

REFERENCES:
patent: 5751655 (1998-05-01), Yamazaki et al.
patent: 6678832 (2004-01-01), Gotanda
patent: 09-180438 (1997-07-01), None
patent: 2000-22279 (2000-08-01), None
patent: 2001-0033509 (2001-04-01), None

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