Memory control apparatus for accessing an image memory in cycle

Details Memory control apparatus for accessing an image memory in cycle Memory control apparatus for accessing an image memory in cycle

1991-02-07

1992-03-03

Lee, Thomas C.

Boots, shoes, and leggings

3642372, 3642222, 3642384, 364270, 3642701, 3642703, 3642705, 3642706, 3642716, 364271, 364284, G06F 1300, G06F 1200

Patent

active

050939025

ABSTRACT:
An operation of a CPU is defined by a predetermined clock. An image memory stores in or read-out image data to be displayed. A display controller connects between the CPU and the image memory, and receives a command from the CPU during an access period set by time-dividing a display period and for controlling a write or read operation of the image data with respect to the image memory. A timing signal generator generates a reference pulse for representing a relationship between the clock for defining the operation of the CPU and the access period. An operation state detector receives the reference pulse generated by the timing signal generator and an access control signal output from the CPU, and detects a state of the CPU with respect to the access period. A wait signal generator generates a wait signal to the CPU, in accordance with a detection result from the operation state detector.

REFERENCES:
patent: 3648250 (1972-03-01), Low et al.
patent: 4065809 (1977-12-01), Matsumoto
patent: 4150429 (1979-04-01), Ying
patent: 4156904 (1979-05-01), Minowa et al.
patent: 4415985 (1983-11-01), McDaniel et al.
patent: 4500956 (1985-02-01), Leininger
patent: 4589089 (1986-05-01), Frederiksen
patent: 4595951 (1986-06-01), Filliman
patent: 4604615 (1986-08-01), Funahashi
patent: 4691295 (1987-09-01), Erwin et al.
patent: 4694392 (1987-09-01), Ballard et al.
patent: 4803475 (1989-02-01), Matsueda
patent: 4845662 (1989-07-01), Tokumitsu
European Patent Office Search Report with Translation.

Affiliated with

Also associated with

Rating

Memory control apparatus for accessing an image memory in cycle does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory control apparatus for accessing an image memory in cycle , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory control apparatus for accessing an image memory in cycle will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-277765