Memory control apparatus for a CRT controller

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340723, 340799, 364518, G06F 314

Patent

active

047018640

ABSTRACT:
A memory control apparatus for a CRT controller in which the same data from a data input circuit is loaded into a plurality of addresses of a buffer memory for storing drawing data, the address of the buffer memory being automatically updated. X- and Y- address generators update address data in response to pulses from X- and Y-axis pulse generators. A microprocessor supplies to a register the width of the X and Y thickness of an address to be updated, coordinate data representing a write start point to the address generators, and the drawing data to be written to a data input circuit. The memory can then be updated in units specified by the X and Y thickness of the picture element.

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patent: 4434503 (1984-02-01), Tanaka et al.
patent: 4517654 (1985-05-01), Carmean
patent: 4570161 (1986-02-01), Kummer et al.
patent: 4580230 (1986-04-01), Jones et al.

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