Memory configuration of a composite memory device

Details Memory configuration of a composite memory device Memory configuration of a composite memory device

2000-07-31

2002-01-01

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189040, C365S230060

Reexamination Certificate

active

06335883

ABSTRACT:

FIELD OF THE INVENTION:
This invention is generally related to a memory device of a whole category of electronic equipment aboard a computerized personal organizer, a handset, a voice recognition device, a voice memory device, and a computer etc. and more particularly related to a composite memory system of a flash memory device.
BACKGROUND OF THE INVENTION
There are many kind of memory devices, for example, mask ROM, erasable programmable read-only memory (EPROM), flash memory and so on. The mask ROM is sintered information data of control command etc in accordance with specifications of users with a production process. Therefore, the mask ROM is unable to rewrite the sintered information data after production. The EPROM is capable of erasing information data by irradiation with ultraviolet lights. However, the EPROM is also unable to electrically erase and rewrite the information data. Therefore, the flash memory device is receiving attention as one of a memory device among the electronic industry. Because of this, the flash memory device is becoming prevalent as an alternative memory device of the mask ROM and the EPROM.
As an electrically erasable memory device, there is an electrically erasable programmable read only memory (EEPROM). Erase operation of the conventional EEPROM is generally based upon one bit unit. On the other hand, erase operation of the flash memory is based upon block unit. Therefore, by the adoption of an erasing by block unit or being one unit of 1 bit, the flash memory device is paid attention as the next generation alternative memory of dynamic random access memory (DRAM) that the integration of the flash memory is far in excess of one of the DRAM market.
Furthermore, the flash memory has obtained a great support from user because of advantages that flash memory is capable of rewriting the data under on board and of being debugged until just before shipment.
Referring to
FIG. 1
, one of conventional prior arts in a memory system includes a flash memory such a single memory array
2
. The memory array
2
has 4 M bits and is divided into plural sector. When the data in the memory element is distinguished under the control of CPU (not shown), the data is sequentially erased with sector unit from the first sector in the memory array
2
or with sector unit from selected sectors.
Address signal A
0
-A
18
are applied an X decoder
6
and an Y decoder
8
with via an address latch
4
. The X decoder
6
selects word line in the memory array
2
. And also the Y decoder
8
selects bit line in the memory array
2
via an Y gate/sensing amplifier
10
.
Programming voltage generator
14
generates a programming voltage for writing data in the memory device
2
. Erase voltage generator
16
generates an erase voltage for erasing data in the memory device
2
. The programming voltage generator
14
and the erase voltage generator
16
output the programming voltage and the erase voltage into the X decoder
6
, the Y decoder
8
, and the memory array
2
each other.
An input/output buffer
20
and a data latch
18
are employed for input or output of data. A timer
22
and a system control register
24
are also employed in this system. The system control register
24
input a write enable signal (/WE), an output enable signal (/OE), a chip enable signal (/CE) and voltage supply, Vcc, GND as control signals. The /WE signal is a start signal of the writing operation of the memory array
2
. The /OE signal is a start signal of the reading operation of the memory array
2
. Further, the /CE signal is a select signal whether the device
1
is selected or the other device is selected.
As for a flash memory, writing operation and erasing operation requires long time in comparison with reading operation. Therefore, a memory device is ideal if the CPU or the other controllers are capable of carrying out the reading operation of the data in the memory array
2
when the other area of the memory array
2
is written or erased under aboard a circuit board.
However, the memory device
1
as shown
FIG.1
can not carry out above mentioned parallel processing.
The 4 M bits capacity's flash memory
2
is formerly used. For example, when the above standard capacity's flash memory
2
is installed as a memory array and the size of software is bigger, the memory array
2
becomes lacking in memory capacity. Therefore, if the large size software is employed, the memory device needs to install a flash memory of the larger capacity. However, it is connected to a cost up to install the memory of the needlessly large capacity.
Thereupon, it is conceivable to employ the plural device as shown
FIG. 1
in order to solve the above problem. Still furthermore, in this case, space savings is not able to be materialized, beside a cost goes up by setting up the same plural memory device.
A concurrent flash memory system such as disclosed in a specification of AT29C432 made of ATMEL Company. The contents of this reference being incorporated herein by reference. The above concurrent flash memory employs the two different type memories that are EEPROM and flash memory in a single device. The concurrent flash memory system of the ATMEL is capable of reading the data of the EEPROM while writing operation of the flash memory in one device.
However, the present inventor identified that the system of ATMEL requires the long time erasing the data on the memory device. Because the EEPROM employed by the system of ATMEL is possible only the writing and also erasing with one bit unit. Accordingly, one sector of the flash memory is 8K byte unit and EEPROM of ATMEL unable to store comparatively large data such as a voice data to one sector. The EEPROM requires comparatively long time to erasing operation when the large size data such as voice etc. is stored and located in astride to plural sector of the flash memory.
Furthermore, the present inventor also identified that conventional erasing operation of the data on a memory requires long time in order to erase by the sector unit. The conventional erasing operation is a single sector erasing mode and a plural sector erasing mode. Although the plural sector erasing mode can erase some number of sectors on the flash memory, the selected plural sector is erased to each sector in turn.
Although the flash memory has a batch erasing mode, the batch erasing mode has erased to the data that does not want to erase.
SUMMARY OF THE INVENTION
To solve the above and other problems, according to one aspect of the present invention, A composite flash memory device includes a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.
According to another aspect of the present invention, a composite flash memory device according to claim
1
, further includes a selector selecting an single sector erasing mode which the sectors of the flash memory device are erased by a sector unit and a simultaneously plural sector erasing mode that simultaneously erases the sectors of a regular range in the plural sector flash memory device.


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STMicroelectronics, “Advanc

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