Memory configuration for unsynchronized input and output data st

Details Memory configuration for unsynchronized input and output data st Memory configuration for unsynchronized input and output data st

1989-05-24

1990-08-21

Shepperd, John W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358148, 358337, 360 362, H04N 514, H04N 595

Patent

active

049511432

ABSTRACT:
Circuitry is disclosed for regenerating a digital output stream referenced to an output timing signal from a digital input stream referenced to an input timing signal wherein the input and output timing signals are typically unsynchronized. Both the digital input stream and a delayed version of the input stream alternately serve as inputs to a dual-port memory. The output port of the memory emits the output stream under control of the output timing signal. Whenever the output stream is being transferred from the dual-port memory to an output buffer, the storing of data through the input port of the memory is temporarily suspended. In order to ensure that no input data is lost, the delayed input stream is presented to the memory after interrupt of the memory by the output timing signal. Prior to the interruption, the input port receives its input directly from the input stream. The delay interval is chosen to be commensurate with the output timing signal to preserve data input into the memory.

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