Memory configuration circuit and method

Details Memory configuration circuit and method Memory configuration circuit and method

1997-12-02

1998-11-03

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 36518908, G11C 800, G11C 700

Patent

active

058319255

ABSTRACT:
A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.

REFERENCES:
patent: 4354256 (1982-10-01), Miyasaku
patent: 5161124 (1992-11-01), Love
patent: 5483497 (1996-01-01), Mochizuki et al.
patent: 5596740 (1997-01-01), Quattromani et al.
patent: 5619471 (1997-04-01), Nunziata

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