Memory component with short access time

Details Memory component with short access time Memory component with short access time

2001-01-31

2002-05-14

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S063000, C365S051000

Reexamination Certificate

active

06388944

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a memory component having a cell array with a plurality of memory cells configured such that a number of bits are synchronously accessible.
In the case of memory components which are clocked synchronously, a specific number of stored bits are to be accessed simultaneously. As a rule, the number is eight, sixteen or thirty-two bits. In this context, “simultaneously” means that all bits which are to be read synchronously have to be brought to an output of the memory component within a predefined, fixed period of time, and from the output they are transferred further as an “information packet.” This period of time is typically in the range of nanoseconds.
In an electronic data processing system, such as e.g. a computer, the maximum clock frequency is limited by that unit which requires the maximum time for performing a process step. Thus, no unit is allowed to require significantly more time than the rest of the units for performing a process step. This means, inter alia, that the access time to a desired number of bits in a memory chip must not exceed the time of one clock cycle. If this were the case, then an additional clock cycle would be required until the information packet were conveyed further, since the information packet waiting at the output of the memory chip can only be conveyed further clock cycle by clock cycle. The processing units which are coupled to the memory component and require this information packet in order to perform their work would each have their work interrupted for the length of one clock cycle.
The access time required both when reading and when storing bits is thus a parameter whose value should be as small as possible.
FIG. 3
shows a schematic structure of a cell array
1
of a memory component according to the prior art. The cell array
1
includes a plurality of cell array strips
2
which are separated from one another by local data line strips
3
which are parallel to the cell array strips
2
and are adjacent on both sides. The cell array strips
2
essentially include a plurality of memory cells
7
. The local data line strips
3
have a plurality of local data lines
4
. The cell array
1
additionally has output amplifiers
6
to which a main data line
5
is in each case connected. This main data line
5
runs perpendicularly both to the cell array strips
2
and to the local data line strips
3
.
If a specific memory cell
7
is to be accessed, then it must be activated. To that end, a plurality of word lines
11
are provided, which run parallel to the local data line strips
3
and within a specific cell array strip
2
. Furthermore, a plurality of column lines
12
are provided, which run parallel to the main data lines
5
and intersect the word lines
11
at crossover points
13
. Each memory cell
7
can be assigned to one of the crossover points
13
in an unambiguous manner. The activation of a crossover point
13
takes place through the activation of the corresponding word and column line
11
,
12
. If the crossover point
13
is activated, then the assigned memory cells
7
can be accessed.
FIG. 5
shows a schematic illustration of the path covered by a bit when it is read from a memory component or written to a memory component. Once a bit stored in a memory cell
7
has been activated via a word line
11
and a column line
12
(cf.
FIG. 4
) it is brought via a bit line
8
to a preamplifier
9
, which is provided on a local data line
4
of a local data line strip
3
and constitutes a connecting element between the bit line
8
and the local data line
4
. The bit amplified by the preamplifier then passes via the local data line
4
to a switch
10
, which lies on a main data line
5
and constitutes a connecting element between the local data line
4
and the main data line
5
. This switch
10
forwards the signal via the main data line
5
to an output amplifier
6
, which raises the signal to a desired output level and subsequently forwards it to an output of the memory chip.
In the case of Synchronous Dynamic Random Access Memory chips (SDRAMs) which synchronously access sixteen bits, it is customary to assign in each case four memory cells
7
to a specific crossover point
13
(cf. FIG.
4
). Thus, if a crossover point
13
is selected by way of the activation of the corresponding word line
11
and/or column line
12
, then the associated four memory cells
7
are activated and the bits stored therein are brought via the bit line
8
to the respective preamplifiers
9
, or bits to be stored are delivered via the preamplifiers
9
to the memory cells
7
.
Thus, four bits are read or written through the activation of a specific crossover point
13
. This means that in the event of an access to sixteen bits, precisely four crossover points
13
, i.e. precisely two word lines
11
and two column lines
12
, have to be activated.
In order to avoid data collisions on the bit lines and the local data lines, care must be taken, therefore, to ensure that two adjacent cell array strips
2
or two word lines
11
within the same cell array strip
2
are never activated simultaneously. This is indicated in
FIG. 3
by the arrow brackets A and B, which each represent one of the possible combinations of activated cell array strips
2
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory component which overcomes the above-mentioned disadvantages of the heretofore-known memory components of this general type and which minimizes the access time to a desired number of bits in the event of a synchronous access.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory component, including:
a cell array having a plurality of memory cells disposed in the cell array, the cell array being configured such that n bits are synchronously accessible in a synchronous memory access, n being an integer number;
a plurality of bit lines connected to respective ones of the memory cells;
a plurality of preamplifiers connected to respective ones of the bit lines;
a plurality of local data lines connected to respective ones of the preamplifiers;
a plurality of switches connected to respective ones of the local data lines;
a plurality of main data lines connected to respective ones of the switches;
a plurality of output amplifiers connected to respective ones of the main data lines; and
the switches being disposed such that a longest possible propagation time of a bit in given ones of the local data lines used for the synchronous memory access is shorter, the further away from associated ones of the output amplifiers the given ones of the local data lines are relative to further ones of the local data lines which are simultaneously required for the synchronous memory access.
In other words, the object of the invention is achieved with a memory module having a plurality of memory cells disposed within a cell array, the cells are in each case connected via a bit line to a preamplifier and, from the latter, via a local data line and a main data line connected to the local data line by a switch, to an output amplifier, a number of n bits being accessed synchronously, wherein switches are disposed in such a way that the longest possible propagation time of a bit in the local data lines is shorter, the further away from the output amplifiers the local data lines are relative to the other local data lines which are simultaneously required in the event of a synchronous memory access.
In accordance with another feature of the invention, the cell array is formed of a plurality of cell array strips; and local data line strips are disposed parallel to one another and adjacent on both sides of the cell array strips such that the cell array strips are separated from one another by the local data line strips.
In accordance with yet another feature of the invention, the local data line strips include at least four of the local data lines.
In accordance with a further feature of the invention, the mai

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