Memory compiler interface and methodology

Details Memory compiler interface and methodology Memory compiler interface and methodology

1998-08-03

2002-06-11

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

Of peripheral device

C703S027000, C716S030000, C710S016000, C717S152000, C717S152000

Reexamination Certificate

active

06405160

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a memory compiler for use in designing integrated memory arrays from user specifications and, more particularly, to a stand alone memory interface (SAMI) and methodology for use with a memory compiler to provide a user with a data file of any type of integrated memory circuit design which the user desires, such as SRAM, ROM, Register File, Dual Port, Synchronous or Asynchronous memory, etc.
One methodology used in the past, was to actually manufacture a user desired memory array in integrated circuit form and then test the memory array to determine if it met the user specifications. If not, another memory array would be manufactured and again tested. Several iterations could be gone through before the user would be satisfied with the operation of the memory array. This process was not only time consuming but not cost effective from the manufacturers stand point.
Another methodology of memory compilers is based upon a Tiling system. In this methodology a memory array of a given configuration, i.e., so many words and bits per word is provided with a given fixed periphery to drive the memory array. If the periphery requires, for example, a word-line buffer one of several buffers are selected. A fixed number of buffers are available to be selected, like tiles used in laying a floor plan, i.e., the circuit manufacture would have available a small buffer, a medium buffer, large buffer or even an extra-large buffer to use. The software compiler methodology would then determine from the size of the memory array to determine what size buffer to use to drive the array. Whichever size buffer has the driving capability closest to the driver requirement is placed, like tiles, into the compiled circuit. Thus, the pieces comprising the pheriphery driver all fit together to drive the memory array but are not optimized for size or speed but only to be “close” in size and driver capability.
Hence, a need exists, for an improved memory compiler methodology for allowing dynamically buffers of a peripheral driver circuit for driving a memory array based on user design specification and which can produce several iterations in real time to allow the user to chose the optimal memory array for his design.


REFERENCES:
patent: 5566127 (1996-10-01), Hoshizaki
patent: 5572482 (1996-11-01), Hoshizaki et al.
patent: 5737270 (1998-04-01), Oppold et al.
patent: 5742814 (1998-04-01), Balasa et al.
patent: 5963454 (1999-10-01), Dockser et al.
patent: 6002633 (1999-12-01), Oppold et al.
patent: 6023565 (2000-02-01), Lawman et al.

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