Memory clocking system

Details Memory clocking system Memory clocking system

1974-09-09

1976-03-09

Fears, Terrell W.

Communications: electrical

Digital comparator systems

307238, G11C 1140

Patent

active

039434966

ABSTRACT:
A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the two different binary values which the memory cells can store, in order to prevent loss of that binary value over a period of time. The reliability of the memory is improved by supplying a refresh signal which includes a plurality of refresh pulses in each memory cycle.

REFERENCES:
patent: 3535699 (1970-10-01), Gaensslen
patent: 3719932 (1973-03-01), Cappon
patent: 3748651 (1973-07-01), Mesnik
patent: 3760379 (1973-09-01), Nibby
patent: 3858185 (1974-12-01), Reed

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