Memory clock pulse generating circuit with reduced peak current

Details Memory clock pulse generating circuit with reduced peak current Memory clock pulse generating circuit with reduced peak current

1983-11-04

1987-02-17

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307601, 307603, 307584, 307578, 307268, 307262, 377 68, H03K 5135, H03K 1728, H03K 17687, G11C 1900

Patent

active

046441840

ABSTRACT:
A dynamic type semiconductor memory device having refreshing function includes a clock pulse generating circuit having a row clock pulse generating section which includes a plurality of cascade-connected delay circuits, a plurality of MOS transistors selectively connected between said delay circuits, and a gate control circuit for changing conduction resistances of the MOS transistors according to the level of a refreshing signal.

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patent: 4496861 (1985-01-01), Bazes
Makoto Taniguchi et al., "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh," IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981.

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