Memory clock generator having multiple clock modes

Details Memory clock generator having multiple clock modes Memory clock generator having multiple clock modes

2007-10-17

2010-02-09

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233120

Reexamination Certificate

active

07660186

ABSTRACT:
An integrated circuit2with a memory4is provided with clock generator circuitry18. The clock generator circuitry18operates in a first mode in which the memory clock signal mclk is generated in dependence upon both the rising edge and the falling edge of a source clock signal sclk. In a second mode of operation the clock generator circuitry18generates the memory clock signal mclk following the rising edge of the source clock signal sclk and then using a self-timing delay path26to trigger the falling edge of the memory clock signal mclk. The first mode of operation can be used during write operations and during read operations at the lowest one of a plurality of different dynamically selectable voltage levels of operation of the memory4. The second mode of self-timed memory clock signal can be used during reads at operating voltages other than the lowest operating voltage.

REFERENCES:
patent: 5432747 (1995-07-01), Fuller et al.
patent: 5905691 (1999-05-01), Tanzawa et al.
patent: 5956290 (1999-09-01), Matsuzaki
patent: 6262940 (2001-07-01), Choi et al.
patent: 6618313 (2003-09-01), Nguyen et al.
patent: 7345950 (2008-03-01), Fujisawa et al.

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