Memory circuits with reduced leakage power and design...

Details Memory circuits with reduced leakage power and design... Memory circuits with reduced leakage power and design...

2008-04-07

2010-02-23

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Powering

Conservation of power

C365S226000, C365S154000

Reexamination Certificate

active

07668035

ABSTRACT:
A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch. Also included are design structures for circuits of the kind described.

REFERENCES:
patent: 5581500 (1996-12-01), D'Souza
patent: 7061794 (2006-06-01), Sabharwal et al.
patent: 2005/0002225 (2005-01-01), Kanehara et al.
patent: 2006/0098474 (2006-05-01), Dang et al.
patent: 2007/0081409 (2007-04-01), Wuu et al.
patent: 2007/0201270 (2007-08-01), Chatterjee et al.
Weste et al , “Principles of CMOS VLSI Design: A Systems Perspective”, Second Edition, pp. 580-582, Addison & Wesley, Redding, 1993.

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