Memory circuit with pipeline processing

Details Memory circuit with pipeline processing Memory circuit with pipeline processing

1991-12-27

1996-01-30

Chan, Eddie P.

Boots, shoes, and leggings

395436, 364DIG1, 3642492, 3642592, 3642595, G06F 1316, G06F 506, G11C 700

Patent

active

054887127

ABSTRACT:
A first-in, first-out (FIFO) type buffer circuit is positioned to hold write-data between a random access memory and a system data bus. A shift circuit is positioned between an address calculation circuit and a pointer circuit. The system data bus is connected to an output of the FIFO buffer circuit or a read-data circuit of the random access memory dependent on an operation mode between writing and reading modes, and the pointer circuit is connected to the address calculation circuit or the shift circuit dependent on the operation mode. Accordingly, pipeline control is realized, even if the data transfer and the memory processing are reversed in order between the writing and reading modes.

REFERENCES:
patent: 4538226 (1985-08-01), Hori
patent: 4827405 (1989-05-01), Kiuchi
patent: 5058076 (1991-10-01), Kiuchi
patent: 5093809 (1992-03-01), Schmitt-Landsiedel et al.
patent: 5379379 (1995-01-01), Becker et al.

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