Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2002-07-26
2003-10-28
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S105000, C365S130000
Reexamination Certificate
active
06639821
ABSTRACT:
The invention relates to a memory circuit, and in particular to a memory circuit with integrated row and column drivers.
A large number of approaches to electronic data storage are currently commercially successful. These include solid state storage, optical storage and magnetic storage. Solid state storage, typically DRAMs, SRAMs, FLASH, EEPROMs, mask ROMs and other types offer the advantages of no moving parts, fast access, high data rate, random access and lower power consumption. They are however relatively expensive. Optical storage, such as CD, mini disk, DVD or optical tape formats have a low cost per bit and are easy and cheap to replicate. However, they only achieve the low costs per bit at high volumes, and further suffer from the disadvantage of relatively long access times, low data rates, bulk and only quasi-random access. Magnetic storage such as hard or floppy disk drives have similar properties to optical storage, although frequently with lower data densities.
There has therefore been an on-going desire to find mass storage technology that achieves the benefits of the solid state approaches mentioned above but at lower cost.
A number of approaches to achieving low cost solid-state memory have been proposed. One proposal is to replace crystalline semiconductor memory structures such as DRAMs and SRAMs with an alternative structure using a simple cross-over to achieve a memory element at each cross-over. Such structures are sometimes known as anti-fuses. Typically, a metal semiconductor metal (MSM) structure is used where a semiconductor material such as amorphous silicon, silicon-rich silicon nitride or a polymer semiconductor is sandwiched between two metal layers. A memory array is then formed using the semiconductor layer to separate a grid of metal tracks running in one row direction from an overlying grid of metal tracks running othogonally, in a column direction. By addressing a specific row and a specific column, it is possible to access the MSM device at the cross-over point between the tracks.
In order to ensure that only the device at the cross-over is read, it is necessary to provide suitable driver circuitry to ensure only the device at the cross-over point is read. Further, there is a need to define the device itself to allow it to switch between two states with electrically different properties.
The advantage of the cross-over structure is its small size. Assuming the smallest lithographic feature size to be F, a single cross-over element can be fitted into an array of for F
2
. This is because each of the orthogonal metal grids may have a line width of F and an inter-line spacing of F which results in an area of each of the cells of (2F)
2
. Alternative memory cells based on transistors occupy at least double this.
Suitable structures are known, for example from WO 96/19837 to Philips Electronics NV.
An example of an alternative approach which aims at a high density is that described in U.S. Pat. No. 4,646,266 to Ovshinsky et al. In this approach, multiple layers of cross-over structures are used together with driver electronics arranged generally around the multiple layers. However, the complexity of the driver and the area required for the driver circuits is considerable.
Moreover, the improvement in the size of the cell using cross-over structures is not enough to offset the larger feature size used in such thin-film processes as compared with conventional processes used to fabricate conventional transistors.
Furthermore, it is not sufficient merely to provide memory cell arrays. It is also necessary to provide row and column drivers and these are generally much larger than individual memory cell elements.
A further device is U.S. Pat. No. 4,442,507 to Roesner which describes an electrically programmable read only memory in which a memory cell array is stacked above a semiconductor substrate. Row electrodes and column electrodes each extend across the full width of a memory cell array and individual memory cells are defined at the crossing points. Vias provided at the ends of the row and column electrodes extend downwards through the memory cell array to a driver electronics layer provided on the semiconductor substrate.
It is an object of the present invention to further improve memory cell density in a memory cell array.
According to the invention, there is provided a memory device comprising: a substrate extending in a plane; an array of memory elements arranged in a plurality of rows and a plurality of columns arranged substantially parallel to the plane of the substrate and over a predetermined area of the substrate; a plurality of row conductors extending along the rows of memory elements and connecting to the memory elements of the respective rows; a plurality of column conductors extending along the columns of memory elements and connecting to the memory elements of the respective columns; a plurality of driver cells containing drivers for driving the row and/or column conductors, arranged in a layer between the memory array and the substrate, and an insulating layer between the driver cells and the array of memory cells, a plurality of conductors passing through the insulating layer distributed over the predetermined area connecting the driver cells to corresponding row or column conductors.
Thus, in the invention drivers are arranged in an array underneath the memory array.
Accordingly, the drive electronics can use most or all of the area of the array of memory elements, saving space.
Preferably, the driver cells each include a column driver. The row drivers may be incorporated into the same cells; alternatively, the row drivers may be arranged around the array of memory elements and the driver cells under the array of memory elements may provide the column drivers.
Preferably, the array of memory elements is spaced from the array of driver cells by an insulating layer, and via holes through the insulating layer are provided to connect the driver cells with column conductors of the array of memory elements.
Conveniently, an insulating layer is provided between the array of driver cells and the array of memory cells, and conductive vias may connect the column drivers of the driver cells with corresponding column conductors.
Preferably, each column of driver cells underlies a number of column conductors and each column driver in each column of driver cells is connected to a different one of the number of column conductors. In this way, each column conductor may be connected to a corresponding column driver.
Conveniently, the row drivers may be arranged outside the area of the memory array.
In a particularly preferred embodiment of the invention, instead of a single array of memory elements, a stack comprising a plurality of such arrays is provided, each array including a plurality of rows and columns of memory elements arranged superstantially parallel to the planes of the substrate.
Preferably, each column driver drives a column in exactly one of the stack of arrays and not in other arrays.
In order to provide passages for vias between drivers and column conductors in layers other than the lowest layer of the stack, lower layers of the stack preferably have gaps wherein no memory elements are defined. Vias may pass through these gaps to connect column drivers on one side of the gap to memory array layers on the other side of the gaps.
Each row driver may drive a row in each of the stack of arrays of memory elements. This allows for easier connection.
Alternatively, each row driver may drive a row in a single one of the layers. In this way, row addressing does not need to drive the capacitance of rows in each of the layers to thereby speed up access times.
The invention also relates to a method of manufacturing a memory device on a substrate extending in a plane, including defining an array of driver cells including at least column drivers over the substrate; depositing an insulating layer over the array of driver cells; depositing a plurality of column conductors over the insulating layer; defining an array of memory elements arrange
Elms Richard
Hur Jung H.
Waxler Aaron
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