Memory circuit with an improved output control circuit

Details Memory circuit with an improved output control circuit Memory circuit with an improved output control circuit

1984-07-13

1987-01-06

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

365189, 365194, 365241, G11C 1140

Patent

active

046352341

ABSTRACT:
A memory circuit of the type having a plurality of output circuits whose peak currents can be reduced. A plurality of timing signals are generated at different time points, and applied to sequentially enable the plurality of output circuits.

REFERENCES:
patent: 4425633 (1984-01-01), Swain
patent: 4503490 (1985-03-01), Thompson

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