Memory circuit with a connection layout and a method for testing

Details Memory circuit with a connection layout and a method for testing Memory circuit with a connection layout and a method for testing

1997-07-08

1999-09-07

Nelms, David

Static information storage and retrieval

Interconnection arrangements

365201, 36518903, G11C 506

Patent

active

059497017

ABSTRACT:
A memory circuit is equipped with a first integrated circuit including a first set of terminals which are connected to a bus and a second integrated circuit including a second set of terminals which are connected to the bus. The signal lines, which one-to one connect the terminals in the first set of terminals to the terminals in the second set of terminals, are arranged so that no pair of signal lines connected to adjacent terminals in the first set of terminals is connected to an adjacent pair or terminals in the second set of terminals.

REFERENCES:
patent: 5561628 (1996-10-01), Terada et al.
"IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE St 1149. 1-1990.

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