Memory circuit receivers activated by enable circuit

Details Memory circuit receivers activated by enable circuit Memory circuit receivers activated by enable circuit

2007-01-30

2007-01-30

Lam, David (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S233100, C365S194000

Reexamination Certificate

active

11013582

ABSTRACT:
A memory circuit comprises an enable circuit and a receiver. The enable circuit is configured to receive an internal clock signal and provide an enable signal having a first logic level and a second logic level. The receiver is configured to be activated in response to the first logic level of the enable signal and deactivated in response to the second logic level of the enable signal.

REFERENCES:
patent: 5953286 (1999-09-01), Matsubara et al.
patent: 6208582 (2001-03-01), Kanda et al.
patent: 6265947 (2001-07-01), Klemmer et al.
patent: 6285625 (2001-09-01), Vogley
patent: 6360085 (2002-03-01), Walley
patent: 6759879 (2004-07-01), Fischer et al.
patent: 6816994 (2004-11-01), Schoenfeld et al.
patent: 2002/0055342 (2002-05-01), Walley

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