Memory circuit having a plurality of input signals

Details Memory circuit having a plurality of input signals Memory circuit having a plurality of input signals

1994-02-02

1994-12-27

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 326 95, G11C 800

Patent

active

053771583

ABSTRACT:
A multi-input memory circuit including a first input gate for selecting one of a plurality of data signals, a first inverting gate for receiving the output of the first input gate as an input, a first feedback gate, which has a structure of a vertical lamination inverter, receives a plurality of clock signals, inverted signals of those clock signals and the output of the first inverting gate, and has its output terminal connected to the output terminal of the first input gate, and a second input gate, which has a vertical lamination inverter structure, and receives a plurality of clock signals, inverted signals of those clock signals and the output of the first input gate, and a second feedback gate, which has a horizontal lamination inverter structure, receives a plurality of clock signals, inverted signals of those clock signals and the output of the second inverting gate, and has its output terminal connected to the output terminal of the second input gate. With this structure, a system of matching the phases of control signals for the individual gates with one another is latently incorporated in the multi-input edge-trigger type memory circuit, thereby preventing data dropout.

REFERENCES:
patent: 5107465 (1992-04-01), Fung
patent: 5173626 (1992-12-01), Kudon
patent: 5229965 (1993-07-01), Inoue
K. Furuya et al., "Introduction to Fault Tolerance", Ohm Ltd. (Japan), Sep. 15, 1988.

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