Memory circuit having a memory reset and recovery controller

Details Memory circuit having a memory reset and recovery controller Memory circuit having a memory reset and recovery controller

1983-09-27

1987-01-27

Moffitt, James W.

Static information storage and retrieval

Addressing

365154, 365203, G11C 700, G11C 1140

Patent

active

046398996

ABSTRACT:
A memory circuit for storing data words including a core memory having a matrix of rows and columns of core cells which store bits of the data words, a row address decoder circuit for driving the rows, and a control signal generator, operative over one reset period and one recovery period, for controlling the columns and the row address decoder circuit to simultaneously charge the contents of the entire core memory to one data state.

REFERENCES:
patent: 4301535 (1981-11-01), McKenny
patent: 4349894 (1982-09-01), Caudel

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