Memory circuit for suppressing bit line current leakage

Details Memory circuit for suppressing bit line current leakage Memory circuit for suppressing bit line current leakage

2002-11-26

2003-09-30

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185210, C365S185290, C365S185300

Reexamination Certificate

active

06628545

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
BACKGROUND ART
Memory devices are known in the art for storing electronic data in a wide variety of electronic devices and applications. Electronic memory, for example, is widely used in a variety of commercial and consumer electronic products. A typical electronic memory device comprises a plurality of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line, and where each memory cell defines a binary state, i.e., either a zero (“0”) bit or a one (“1”) bit. A column of memory cells are also connected together, normally by connecting the respective drain or source terminal of each memory cell in the column along the same bit line.
In certain memory devices, a memory cell may be defined as either being a “programmed” cell or an “erased” cell. According to one particular convention, a programmed cell is representative of a “0” bit, and an erased cell is representative of a “1” bit. The state of a memory cell is often determined by sensing the current drawn by the memory cell. For example, to ascertain the current drawn by a particular memory cell, the drain terminal of the memory cell is connected to a sensing circuit, the source terminal of the memory cell is connected to ground, and the control gate of the memory cell is selected. With these connections established, the sensing circuit attempts to detect the current drawn by the memory cell. The sensed memory cell current can then be compared against a reference current to determine whether the memory cell is an erased cell or a programmed cell. For example, if the sensed memory cell current exceeds the reference current, the memory cell is considered an erased cell (corresponding to a “1” bit). However, if the sensed memory cell current is below the reference current, the memory cell is considered a programmed cell (corresponding to a “0” bit).
As described above, the drain terminals of the memory cells in the same column are connected together along a common bit line. In certain cases, this common connection creates a problem during detection of current drawn by a selected memory cell. The problem arises when, for example, one or more of the other memory cells along the same bit line conduct current even though these other memory cells are not selected. Thus, the sensing circuit which attempts to detect the current drawn by the selected memory cell may also detect the current, if any, drawn by the other memory cells along the same bit line since the drain terminals of the memory cells are connected together along the same bit line. In these cases, the current for the selected memory cell may be sensed incorrectly, since the current drawn by the other memory cells contribute to the sensed current. Thus, the reliability of verification of the erased or programmed state of memory cells in memory devices is significantly reduced. Known approaches for dealing with this problem involve lengthy and slow procedures. Accordingly, there exists a strong need in the art to overcome deficiencies of conventional memory circuits, such as those described above, for quickly and reliably detecting memory cell current and for verifying the erased or programmed state of a memory cell during memory operations.
SUMMARY
The present invention is directed to a memory circuit for suppressing bit line current leakage. The present invention addresses and resolves the need in the art for quickly and reliably detecting memory cell current and for verifying the erased or programmed state of a memory cell during memory operations. According to one exemplary embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first and second memory cells may, for example, comprise floating gate memory cells, each having corresponding threshold voltages. According to one embodiment, the threshold voltage of the first memory cell is greater than the threshold voltage of the second memory cell and wherein the memory circuit supplies a source voltage greater than a ground voltage.
The first memory cell has a drain terminal connected to a bit line, and the bit line is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line, which supplies an appropriate voltage to activate the first memory cell. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The source voltage is connected to a source terminal of the first memory cell and to a source terminal of the second memory cell. With this configuration, the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory thereby reducing or eliminating the current drawn by second memory cell during verification of the first memory cell.


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