Memory circuit for alternately accessing data within a period of

Details Memory circuit for alternately accessing data within a period of Memory circuit for alternately accessing data within a period of

1992-11-10

1995-05-16

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523008, 36523004, 36523001, 365233, 365236, 365239, 365194, G11C 700, G11C 800

Patent

active

054167469

ABSTRACT:
A memory circuit includes an input selector for receiving input data serially at an interval of a period T and outputting the input data and an address counter for generating first address data sequentially at an interval of a having period 2T and second address data sequentially at an interval having period 2T. The second address data is delayed a period T from the first address data. The memory circuit of the present invention further includes two memory blocks coupled to the input selector and address counter. One memory block stores even numbered input data in response to the first address data and outputs them at the interval of the period 2T. The other memory block stores odd numbered input data in response to the second address data and outputs them at the interval of the period 2T.

REFERENCES:
patent: 4450538 (1984-05-01), Shirasaka
patent: 4849937 (1989-07-01), Yoshimoto
patent: 5016226 (1991-05-01), Hiwada et al.
"HM63021, 2048-wordx8-bit Line Memory", extract from Hitachi IC Memory Databook 1, Sep. 1990, 12th version, pp. 385-396.
"HM53051, 26144-Wordx4-bit Frame Memory", extract from '90 Mitsubishi Semiconductor Memory RAM Data Book, M5M4C264 C-10, -12-15, Sep. 1990, pp. 397-408.

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