Memory circuit, drive circuit for a memory and method for...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S185260

Reexamination Certificate

active

07599226

ABSTRACT:
A first and second non-volatile memory transistor each have a floating gate electrode and a gate terminal. A first switch is connected between a first drain terminal and a bit line for reading out information, and a second switch is connected between a second drain terminal and the bit line. The first and second switch are designed to selectively couple the first or second drain terminal to the bit line during readout. A drive circuit is designed to write data into one of the transistors and to apply equal signals to the gate terminals of the first and second transistors based on the data, to apply a programming signal at a source terminal of the transistor to be written to and to drive a source terminal of a transistor not to be written to such that a state stored in the transistor not to be written to is not changed.

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patent: 6459616 (2002-10-01), Beauchamp et al.
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patent: 6795347 (2004-09-01), Ausserlechner et al.
patent: 7064985 (2006-06-01), Kuo
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patent: 2003/0189865 (2003-10-01), Ausserlechner et al.
patent: 2004/0042272 (2004-03-01), Kurata
patent: 2007/0189075 (2007-08-01), Ausserlechner et al.
patent: 102 14 898 (2003-10-01), None
patent: WO 02/071408 (2002-09-01), None

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