Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2005-10-14
2008-12-02
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Format or disposition of elements
C365S063000
Reexamination Certificate
active
07460385
ABSTRACT:
In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
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Gruber Wolfgang
Kakoschke Ronald
Schweizer Thomas
Wegertseder Dominik
Brinks Hofer Gilson & Lione
Hur J. H.
Infineon - Technologies AG
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