Memory circuit arrangement for programming a memory cell

Details Memory circuit arrangement for programming a memory cell Memory circuit arrangement for programming a memory cell

2003-01-21

2004-06-08

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185260

Reexamination Certificate

active

06747900

ABSTRACT:

1. Technical Field
The present invention relates generally to the field of semiconductor devices. More particularly, the present invention relates to semiconductor memory devices.
2. Background Art
Memory devices are known in the art for storing electronic data in a wide variety of electronic devices and applications. Electronic memory, for example, is widely used in a variety of commercial and consumer electronic products. A typical memory device comprises a plurality of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line, and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit. For example, a memory cell may be defined as either being a “programmed” cell or an “erased” cell. According to one particular convention, a programmed cell is representative of a “0” bit, and an erased cell is representative of a “1” bit. Typically, the state of a memory cell is determined during a “read” operation by sensing the magnitude of the current drawn by the memory cell, where, for example, a low current draw indicates a “programmed” cell (corresponding to a “0” bit) and a high current draw indicates an “erased” cell (corresponding to a “1” bit).
A typical memory cell may be formed on a semiconductor substrate. For example, a floating gate memory cell comprises an N-type source region formed within a P-type substrate, an N-type drain region formed within the P-type substrate and spaced apart from the source region, a channel region interposed between the source and the drain regions, a floating gate insulated from and spaced a short distance above the channel, and a control gate insulated from and disposed above the floating gate.
According to conventional operation, a memory cell is “programmed” by inducing high energy electron injection onto the floating gate. Electron injection carries negative charge into the floating gate. This injection mechanism is normally induced by connecting the source region and the substrate to ground, applying a high positive voltage to the control gate and applying a high positive voltage to the drain region. The voltage supplied to the control gate creates an electron attracting field while the voltage supplied to the drain region generates high energy electrons, which are attracted to and negatively charge the floating gate. The accumulation of negative charge in the floating gate raises the negative potential of the floating gate, which raises the threshold voltage of the memory cell and reduces current drawn by the memory cell during subsequent read operations, thereby indicating a “programmed” cell (corresponding to a “0” bit).
A number of drawbacks are associated with the conventional approach of programming memory cells. For example, because of the high voltages required for programming a memory cell, large charge pumps may be required in order to supply the requisite high voltages. Large charge pumps have the disadvantage of requiring larger silicon areas in the memory device, thereby increasing fabrication costs and increasing device size, both of which are undesirable. Accordingly, there exists a strong need in the art to overcome deficiencies of conventional memory circuits, such as those described above, for quickly and reliably programming memory cells and for reducing the voltage requirements during programming operations.
SUMMARY
The present invention is directed to a memory circuit arrangement for programming a memory cell. The present invention results in quick and reliable programming of memory cells while reducing voltage requirements during programming operations. According to one exemplary embodiment, a memory circuit comprises a target cell having a drain terminal connected to a bit line, where, for example, a programming operation involving the target cell is to be performed. The target cell may for example, comprise a floating gate memory cell. In the exemplary embodiment, a drain voltage is coupled to the bit line and supplies a voltage greater than the ground voltage, while a gate voltage is coupled to a gate terminal of the target cell and also supplies a voltage greater the ground voltage. A source voltage is coupled to a source terminal of the target cell and supplies a voltage less than the ground voltage, and a substrate voltage is coupled to a substrate of the target cell and also supplies a voltage less than the ground voltage. According this exemplary embodiment, the drain voltage, gate voltage, source voltage, and substrate voltage cause electrons to be generated and attracted to a floating gate of the target cell. As a result, the target cell is programmed. However, since the source and substrate voltages are below the ground voltage, the high voltage requirements at the drain terminal of the target cell for programming the target cell are reduced, when compared to conventional configurations.
In one particular embodiment, the substrate voltage is less than the source voltage. For example, in one embodiment, the substrate voltage is approximately −3 V, while the source voltage is approximately −2 V. In this embodiment, the memory circuit further comprises an unselected cell having a drain terminal connected the bit line. The source terminal of the unselected cell is coupled to the source voltage, while the gate terminal of the unselected cell is connected to ground. The substrate of the unselected cell is also connected to the substrate voltage. According this exemplary embodiment, the difference between the substrate voltage and the source voltage causes the threshold voltage of the unselected cell to be greater than the gate-to-source voltage of the unselected cell. As a result, the unselected cell does not draw current from the bit line, thereby reducing or eliminated leakage current along the bit line during programming of the target cell.
Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.


REFERENCES:
patent: 6243298 (2001-06-01), Lee et al.

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