Memory circuit architecture

Details Memory circuit architecture Memory circuit architecture

1999-09-15

2002-04-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S230060

Reexamination Certificate

active

06373741

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memories made in the form of an array network of memory cells in an integrated circuit. The present invention more specifically applies to DRAMs which store the data (states “0” or “1”) to be stored in memory cells, each formed of a storage capacitor and of a selection MOS transistor. Reference will be made hereafter to the example of a DRAM. It should however be noted that the present invention also relates to other types of memories, for example, SRAMs or EPROMs and, more generally, any array of cells.
2. Discussion of the Related Art
FIG. 1
very schematically shows an example of a cell
1
of a conventional DRAM. Such a cell
1
is formed of a selection MOS transistor T (herein, for example, an N-channel transistor) associated with a data storage capacitor C. The gate g of transistor T is connected to a row WL, called a word line. Drain d of transistor T is connected to a column line LBL, called a local bit line. Source s of transistor T is connected to a first terminal of capacitor C, the other terminal of which is connected to a constant voltage Vp, generally a median voltage (Vdd/2) between high and low supply voltages Vdd and Vss (generally the ground). Terminal s forms the storage node for the data of the memory cell thus formed. Several memory cells shown in
FIG. 1
are associated in an array of word lines and bit columns.
For a cell
1
such as shown in
FIG. 1
to be addressed., the word line WL associated with the gate of transistor T has to be brought to a high voltage, generally high supply voltage Vdd of the array.
If this addressing is linked to a write operation, storage node s is then placed either at the low supply voltage (Vss) of the array if capacitor C is discharged via a bit line LBL connected to the ground, or at potential Vdd if bit line LBL is placed at potential Vdd, signifying a programming to the high state. To simplify the present discussion, the levels described hereabove do not take account of the influence of threshold voltage Vt of transistor T upon the level stored in capacitor C.
If cell
1
is addressed in the read mode, local bit line LBL is precharged to a median potential (Vdd/2) between the two high and low supply potentials Vdd and Vss of the circuit. The stored state “0” or “1” is then determined by comparing the potential of bit line LBL, modified according to the charge of capacitor C, with a reference bit line, also precharged to a level Vdd/2 but not influenced by the storage capacitor.
FIG. 2
very schematically illustrates the use of reference bit lines in a so-called “open” DRAM, in which the reference lines come from a neighboring array of memory cells, distinct from the array containing the addressed cell, as opposed to “folded” memories where the reference line of an addressed cell is formed by the bit line neighboring this cell. The present invention however also applies to folded memories as will be seen hereafter.
In such a memory architecture, a first plane or section P
1
of cells
1
of the type shown in
FIG. 1
is separated from a second memory plane P
2
containing the same type of elementary cells
1
′. Each plane P
1
, P
2
forms by itself an array of memory cells independent from the other, in that it is addressable by different word lines WL
1
, WL
2
. On the bit line side, each memory plane has its own local bit lines LBL
1
and LBL
2
, but shares the read/write or column decoding amplifiers (not shown in
FIG. 2
) with the other memory plane. Hereafter, reference will be made to a read amplifier or column decoder. In practice, each local bit line LBL
1
J
or LBL
2
J
of each memory plane P
1
, P
2
, is connected, via a section selection transistor Ts
1
j
, Ts
2
j
, to a global bit line GBL
1
, GBL
2
, respectively. Global bit lines GBL
1
j
and GBL
2
j
corresponding to columns of the same row j in the two memory planes P
1
and P
2
, they however share a same column decoding amplifier, one of the two lines being used as a reference by the other. Accordingly, memory planes P
1
and P
2
are not addressed simultaneously in the read mode (this is why they are respectively associated with different word lines), each plane being in turns used as a reference plane for the memory cells read in the other memory plane.
For simplification, memory planes P
1
and P
2
have not been completely shown in FIG.
2
. Only one cell for each plane and the section decoding transistor associated with the corresponding local bit line have been shown. The rank of the word lines has been designated by index I while the rank of the bit lines has been designated by index j.
Section selection transistors Ts
1
j
and Ts
2
j
receive, on their respective gates, control signals Seg
1
and Seg
2
which are simultaneously activated.
Assuming a reading of cell
1
at the intersection of lines WL
1
I
and LBL
1
j
, the selection transistor T of this cell is turned on, as well as the transistor Ts
1
j
of selection of the section corresponding to memory plane P
1
. Global bit line GBL
2
j
is then used as a reference bit line for the reading from cell
1
of plane
1
, transistor Ts
2
j
being also turned on to equalize the parasitic elements. The global bit lines are precharged to level Vdd/2 by means of precharge devices (not shown) connected, for the occasion, to first end terminals PL
1
j
, PL
2
j
of lines GBL
1
j
, GBL
2
j
. This precharge may be performed via local bit lines (all transistors Ts being on along the column). Since both global bit lines are precharged to level Vdd/2, the direction of the slight difference (coming from capacitor C of the decoded cell) between their respective levels during the reading determines the state of cell
1
.
It should be noted that signals Seg
1
and Seg
2
simultaneously control the section selection transistors Ts
1
and Ts
2
of all the local bit lines of the memory plane with which these control signals are associated. The column selection in the memory array is generally performed downstream, that is, at the level of the data input-output stages in the memory. These stages (not shown in
FIG. 2
) especially include buffers.
FIG. 3
very schematically shows a conventional example of the read amplifier or column decoder CDEC and of an input-output stage I/O of a memory to which the present invention relates.
Each pair of global bit lines GBL
1
j
, GBL
2
j
, associated to be respectively used by the other as a reference bit line, is sent onto one of the two inputs of a column decoding amplifier A
j
, intended for providing, on an output S
j
, the decoded state of the memory cell from which it has been read. Amplifier A
j
receives control and supply signals generally designated by reference CTRL
j
. Output S
j
of amplifier A
j
is sent, with the respective outputs of several other read amplifiers (for example, A
j+1
), onto an input-output stage I/O
j
for selecting one of the inputs that it receives to provide a single bit B
j
which has been read. Stage I/O
j
is controlled by a bit decoding circuit BDec, and is associated with several other input-output stages receiving output signals from different read amplifiers, each stage I/O providing a bit of a word (for example, of 16 bits) of the memory.
The bulk of a column decoding amplifier A
j
of a conventional DRAM generally leads to having these amplifiers aligned two by two in the column direction to have a sufficient width to ensure all the connections required by the transistors constitutive of these amplifiers. Thus, in
FIG. 3
, two amplifiers A
j
and A
j+
1
have been shown to be aligned in the column direction (vertical direction in the drawing).
A problem which is raised in the making of DRAMs is the necessary compromise between the signal-to-noise ratio received by the column decoding amplifiers CDEC (
FIG. 3
) and the number of necessary section decoders SDEC (FIG.
2
), and thus of memory planes P. Indeed, the higher the desired signal-to-noise ratio for the read amplifiers, the more the number of memory planes and, accordingl

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