Memory circuit and method of generating the same

Details Memory circuit and method of generating the same Memory circuit and method of generating the same

2007-03-06

2007-03-06

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S191000, C365S198000, C365S230030

Reexamination Certificate

active

11011116

ABSTRACT:
A memory circuit10includes: a feed-through input terminal13for inputting a signal different from a signal to be inputted when reading and writing memory cells; an intermediate buffer circuit14provided between regions where the memory cells are arranged, for relaying the signal inputted through the feed-through input terminal13; and a feed-through output terminal15for outputting the signal relayed by the intermediate buffer circuit14. Connections between the feed-through input terminal13and the intermediate buffer circuit14and between the intermediate buffer circuit14and the feed-through output terminal15are established by feed-through wires16, 17, respectively. The feed-through wires16, 17are not connected to either a wire to be used when reading and wiring the memory cells, or the memory cells.

REFERENCES:
patent: 6831356 (2004-12-01), Terada et al.
patent: 60-025251 (1985-02-01), None
patent: 63-091895 (1988-04-01), None

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