Static information storage and retrieval – Addressing – Combined random and sequential addressing
Patent
1995-06-07
1996-12-24
Lane, Jack A.
Static information storage and retrieval
Addressing
Combined random and sequential addressing
365221, 365236, 365239, G11C 804
Patent
active
055879624
ABSTRACT:
A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
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Dolait Jean-Pierre
Frantz Gene A.
Hashimoto Masashi
Moravec John V.
Bassuk Lawrence J.
Donaldson Richard L.
Havill Richard B.
Lane Jack A.
Texas Instruments Incorporated
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