Memory circuit

Details Memory circuit Memory circuit

1976-01-02

1977-06-21

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307284, 307288, 307313, 340173R, G11C 1504, G11C 1140

Patent

active

040314138

ABSTRACT:
A memory circuit for providing a zero OFF-holding power under the logical control of three inputs comprises a memory cell including a semiconductor element circuit of equivalently four PNPN layer structure and a logical input section including at least one PNP transistor and NPN transistor with the collector of the PNP transistor connected to the base of the NPN transistor. The NPN transistor in the logical input section has its collector connected to the control gate of the memory cell, and logical input signals are applied to the emitter and base of the PNP transistor and the emitter of the NPN transistor in the logical input section, respectively.

REFERENCES:
patent: 3740730 (1973-06-01), Ho et al.
patent: 3806894 (1974-04-01), Nev et al.
patent: 3918033 (1975-11-01), Case et al.

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