Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1999-02-24
2001-01-09
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S226000, C711S103000, C711S166000, C711S167000
Reexamination Certificate
active
06172936
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory circuit, such as a flash memory, and particularly to a memory device capable of being switched between asynchronous read operations and clock-synchronous read operations.
2. Description of the Related Art
Semiconductor memory devices offer fast access times, and are utilized in computer systems for main memories and other memories of which fast access times are required. On the other hand, semiconductor memory devices are unsuited to storing large programs and large quantities of data; accordingly, hard disks are used in such large capacity memory applications. Of the various semiconductor memory devices, dynamic RAM is used principally for main memories. DRAM is a volatile memory that loses stored data when the power is shut off, and thus while suited to storing data or programs that are to be held in memory on a temporary basis, it is unsuited to storing the BIOS routine read out during computer boot-up, or other such programs.
Nonvolatile memories have attracted attention for the ability to hold stored data even when the power is shut off. In particular, flash memories that use nonvolatile memory, while presenting a certain limitation in terms of erase operations, are nonvolatile memories which, due to the basic operating principle of such memories, are capable of holding stored data even when power is shut off. Another advantage is faster access times than hard disks and other external memory devices. In computer systems offered in recent years, it has become common practice to store in flash memory the BIOS routine that is read out automatically at computer boot-up.
Operations executed at boot-up of a computer include automatic accessing of the flash memory in which the BIOS is stored and reading of the BIOS data at power-on; reading out the operating system (OS) stored on the hard disk; and placing this data in the dynamic RAM main memory. During subsequent execution of an application program, the OS placed in the main memory is serially read, and application program stored on the hard disk or other external memory device is executed. The dynamic RAM offered in recent years, such as SDRAM, are synchronous memories in which read operations are synchronized with the clock. Burst mode read operation, in which a continuous multiple-bit data stream is output synchronized with the clock, is an indispensable capability in terms of fast reads. Burst reads allow the OS to be read from the main memory at high speeds.
Conventional flash memory, on the other hand, is asynchronous memory, which has to wait for a given access time before reading out data stored at a given address in response to input of the address.
The OS generally consists of a smaller amount of data than does an ordinary application program; thus, as flash memory capacities have become greater, it has become possible to store the OS in flash memory, provided that there is sufficient data capacity to accommodate the OS. Storing the OS in flash memory obviates the need to transfer it to main memory from the hard disk, thereby significantly reducing the time required to boot up the computer. Since conventional flash memory is asynchronous, it is not possible for the system to perform the burst read operation on the flash memory storing the OS that are performed on the main memory. The slowness of read operations to flash memory diminishes the attractiveness of proposals to store the OS and other programs in flash memory.
Accordingly, it is an object of the present invention to provide a flash memory or similar nonvolatile memory circuit that is capable of clock-synchronous read operation.
It is another object of the present invention to provide a flash memory or similar nonvolatile memory circuit that is capable of burst read operation.
Yet another object of the present invention is to provide a flash memory or similar nonvolatile memory circuit that is capable of both clock-synchronous read operation and clock-asynchronous read operation. One other object of the present invention is to provide a flash memory that, viewed from the system end, is capable of conventional clock-asynchronous read operation, that is further capable of clock-synchronous read operation analogous to those for main memory, and that can be switched between the two modes as required.
Yet another object of the present invention is to provide a flash memory capable of being switched as appropriate between asynchronous read operation and burst read operation.
SUMMARY OF THE INVENTION
To achieve the foregoing objects, the present invention comprises a flash memory or similar nonvolatile memory circuit characterized by a constitution that enables read operations in two modes, a clock-synchronous burst read mode and a clock-asynchronous normal read mode, the device being set to normal read mode in response to power on, and being set to burst read mode in response to a control signal instructing the burst read mode. The memory circuit includes a burst mode switching circuit internally. This burst mode switching circuit sets an output circuit to normal read mode in response to the power ON so as to enable read operations not synchronized with the clock after the power ON. In response to a burst mode control signal provided by the system, the burst mode switching circuit sets the output circuit to burst read mode. Thus, the system can perform the burst read to the nonvolatile memory device under the environment analogous to conventional main memory access.
To achieve the foregoing objects, the present invention provides a memory circuit including nonvolatile memory cells, comprising: an output circuit for executing clock-synchronous burst read operation and clock-asynchronous normal read operation of data read from the memory cells, and a burst mode switching circuit for setting the output circuit to the normal read mode in response to power ON, and for setting the output circuit to the burst read mode in response to a specific control signal provided from outside.
According to the above invention, operations are performed in normal read mode when the power is turned on, and are set to burst read mode in response to a control signal instructing the burst read mode, allowing the system to be set to clock-asynchronous operation mode and clock-synchronous operation mode during power-on and subsequent operations.
To achieve the foregoing objects, the present invention further provides a memory circuit capable of being switched in response to a burst control signal between a clock-synchronous first read mode and a clock-asynchronous second read mode, wherein, in the first read mode, address signals are acquired in synchronous with the clock during a first control signal being at activation level, and a plurality of read data are output in synchronous with the clock during a second control signal being at activation level after a prescribed time interval since the first control signal being at the activation level, comprising: a burst mode switching circuit for setting the burst control signal to the second read mode condition when the power is turned on, and for setting the burst control signal to the first read mode condition in response to the first control signal being at the activation level.
According to the above invention, the memory device is forced to operate in clock-asynchronous normal read mode when the power is turned on, and is capable to operate in clock-synchronous burst read mode in response to a burst mode read instruction signal subsequently.
REFERENCES:
patent: 5696917 (1997-12-01), Mills et al.
patent: 5757715 (1998-05-01), Williams et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 0 561 370 (1993-09-01), None
patent: 0 591 009 (1994-04-01), None
Armstrong, Westerman Hattori, McLeland & Naughton
Elms Richard
Fujitsu Limited
Nguyen Vanthu
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