Memory circuit

Details Memory circuit Memory circuit

1976-08-06

1978-01-03

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307213, 307252A, 307252G, 307299A, 307299B, 365180, G11C 1134, H03K 1772

Patent

active

040669157

ABSTRACT:
A memory circuit is comprised of a memory cell of PNPN- equivalent 4-layer construction, a selective input circuit composed of a pair of an NPN transistor and a PNP transistor, and a read-out circuit for reading the information stored in the memory cell. The emitters of the transistors included in the selective input circuit are connected to one of the selective input terminals, the bases thereof to the other selective input terminal, the collector of one of the transistors to the write input terminal of the memory cell, and the collector of the other transistor to the input terminal of the read-out circuit. Thus, both the writing and reading operations are controlled from the same selective input terminal, and power consumption of the selective input circuit in the holding mode is substantially zero.

REFERENCES:
patent: 3918033 (1975-11-01), Case et al.
patent: 3986177 (1976-10-01), Picquendar et al.

Affiliated with

Also associated with

Rating

Memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-282831