Static information storage and retrieval – Addressing – Sequential
Patent
1982-04-12
1984-11-27
Popek, Joseph A.
Static information storage and retrieval
Addressing
Sequential
365193, G11C 1140
Patent
active
044854617
ABSTRACT:
A memory circuit which can perform consecutive write operations at a high speed is disclosed. The memory circuit comprises a plurality of bus lines, a plurality of memory cell groups associated with the respective bus lines, a plurality of latch circuits coupled to the respective bus lines, and means for sequentially supplying the bus lines with write data, in which the write data are stored in the latch circuits and transferred to selected memory cells of the respective memory cell groups.
REFERENCES:
patent: 3846769 (1974-11-01), Shepherd
patent: 4164031 (1979-08-01), Low et al.
Nippon Electric Co. Ltd.
Popek Joseph A.
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