Memory chip having multiple input/output system

Static information storage and retrieval – Addressing – Plural blocks or banks

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36523006, G11C 800

Patent

active

060882840

ABSTRACT:
A memory chip having a multiple input/output system enables a memory to have a .times.n, .times.2n or .times.4n I/O system through a simple fuse mask process by using a single memory chip and reduces the consumption of a cell current while having a memory capacity which is the same as in the .times.n or .times.2n I/O system of the conventional art. The multiple input/output memory chip according to the present invention includes a block selecting unit for receiving a source voltage or a column address lowest bit and thereby selectively activating a first block selection signal or a second block selection signal, a column control unit for receiving a source voltage or a column address lowest bit and thereby selectively activating a first column control signal or a second column control signal, a first bank for simultaneously reading or writing n-bit or 2n-bit data in accordance with the first or second column control signal and the first block selection signal, a second bank for simultaneously reading or writing n-bit or 2n-bit data in accordance with the first or second column control signal and the second block selection signal, and a data bus which is connected with first to third fuses and thereby dividable up to four parts.

REFERENCES:
patent: 5262990 (1993-11-01), Mills et al.
patent: 5305278 (1994-04-01), Inoue
patent: 5629900 (1997-06-01), Hirose et al.

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