Memory chip architecture with high speed operation

Details Memory chip architecture with high speed operation Memory chip architecture with high speed operation

2007-12-04

2009-02-24

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S189030, C365S189180, C365S189080

Reexamination Certificate

active

07495991

ABSTRACT:
A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.

REFERENCES:
patent: 5880987 (1999-03-01), Merritt
patent: 6041013 (2000-03-01), Kohno
patent: 6097640 (2000-08-01), Fei et al.
patent: 6151264 (2000-11-01), Yoo
patent: 6314042 (2001-11-01), Tomishima et al.
patent: 6331955 (2001-12-01), Shin et al.
patent: 6351404 (2002-02-01), Wright et al.
patent: 6353549 (2002-03-01), Merritt
patent: 6385100 (2002-05-01), Noda et al.
patent: 6396766 (2002-05-01), Lee
patent: 6473358 (2002-10-01), Noda et al.
patent: 6473360 (2002-10-01), Ooishi
patent: 6512719 (2003-01-01), Fujisawa et al.
patent: 6541849 (2003-04-01), Roohparvar
patent: 6569727 (2003-05-01), Casper et al.
patent: 6668345 (2003-12-01), Ooishi et al.
patent: 6873563 (2005-03-01), Suwa et al.
patent: 6891772 (2005-05-01), Demone
patent: 6898110 (2005-05-01), Ishimatsu et al.
patent: 6949813 (2005-09-01), Roohparvar
patent: 6996027 (2006-02-01), Shin
patent: 7016255 (2006-03-01), Lee et al.
patent: 7042791 (2006-05-01), Park
patent: 7061941 (2006-06-01), Zheng
patent: 7110321 (2006-09-01), Gibson
patent: 7123497 (2006-10-01), Matsui et al.
patent: 7200067 (2007-04-01), Ahn et al.
patent: 7310258 (2007-12-01), Lee et al.
patent: 2005/0141255 (2005-06-01), Ko et al.
patent: 2002-21177 (2000-01-01), None
patent: 2000-149549 (2000-05-01), None
patent: 2003-100073 (2003-04-01), None
patent: 2000-0062116 (2000-10-01), None
patent: 2002-0061872 (2002-07-01), None
patent: 2003-0001870 (2003-01-01), None
patent: 2004-0022905 (2004-03-01), None

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