Memory chip architecture with high speed operation

Details Memory chip architecture with high speed operation Memory chip architecture with high speed operation

2007-12-18

2007-12-18

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S230030, C365S189030, C365S214000, C365S189080

Reexamination Certificate

active

11323386

ABSTRACT:
A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.

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