Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-07-12
2011-07-12
Landau, Matthew C (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257SE21526, C257SE25013
Reexamination Certificate
active
07977159
ABSTRACT:
In a wafer, a plurality of basic chips F is arranged therein. The basic chip F has a memory capacity of i-mega bytes. By dicing, a memory chip including four basic chips F is cut out of the wafer. The memory chip has a memory capacity of 4×i-mega bytes. A dicing line is interposed between four basic chips F configuring the memory chip, Four basic chips F can change word organization by a control signal individually.
REFERENCES:
patent: 4408875 (1983-10-01), Majima
patent: 4907203 (1990-03-01), Wada et al.
patent: 5506499 (1996-04-01), Puar
patent: 5598033 (1997-01-01), Behlen et al.
patent: 5661662 (1997-08-01), Butts et al.
patent: 5737767 (1998-04-01), Agrawal et al.
patent: 5943254 (1999-08-01), Bakeman et al.
patent: 6055594 (2000-04-01), Lo et al.
patent: 6078096 (2000-06-01), Kimura et al.
patent: 6172409 (2001-01-01), Zhou
patent: 6372554 (2002-04-01), Kawakita et al.
patent: 6417695 (2002-07-01), Duesman
patent: 6424034 (2002-07-01), Ahn et al.
patent: 6594818 (2003-07-01), Kim et al.
patent: 6646342 (2003-11-01), Sakiyama et al.
patent: 6677674 (2004-01-01), Nagao
patent: 6798049 (2004-09-01), Shin et al.
patent: 6901015 (2005-05-01), Shinohara
patent: 6969623 (2005-11-01), Ikeda et al.
patent: 2001/0002179 (2001-05-01), Tomita et al.
patent: 2001/0036738 (2001-11-01), Hatanaka et al.
patent: 2001/0040281 (2001-11-01), Butler
patent: 2002/0136046 (2002-09-01), Kim et al.
patent: 2002/0140107 (2002-10-01), Kato et al.
patent: 2002/0164838 (2002-11-01), Moon et al.
patent: 63-261852 (1988-10-01), None
patent: 1-235264 (1989-09-01), None
patent: 4-157695 (1992-05-01), None
patent: 4-343469 (1992-11-01), None
patent: 4-373169 (1992-12-01), None
patent: 2000-49307 (2000-02-01), None
patent: 2000-195962 (2000-07-01), None
patent: 2000-223657 (2000-08-01), None
patent: 2000223657 (2000-08-01), None
patent: 2000-340746 (2000-12-01), None
patent: 2000-349130 (2000-12-01), None
patent: 2001-176263 (2001-06-01), None
patent: WO 02/082540 (2002-10-01), None
Wang, Memory and Logic Integration for System-in-a-Package, Computer Engineering Department, University of California, Santa Cruz, pp. 843-847.
Tadahiko Sugibayashi, et al., “A 1gB DRAM for File Applications”, ISSCC Digest of Technical Papers, 1995. pp. 254-255.
Crawford Latanya
Kabushiki Kaisha Toshiba
Landau Matthew C
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
LandOfFree
Memory chip and semiconductor device using the memory chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory chip and semiconductor device using the memory chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory chip and semiconductor device using the memory chip... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2620858