Memory cells and memory devices with a storage capacitor of para

Details Memory cells and memory devices with a storage capacitor of para Memory cells and memory devices with a storage capacitor of para

1995-01-31

1997-04-22

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

365149, 36518529, 36518501, G11C 1140

Patent

active

056234422

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The present invention relates to a memory cell and memory device with a storage capacitor of parasitic capacitance and a method of storing information therein. The non-volatile memory device incorporates write and erase functions based on a DRAM where parasitic capacitance associated with bit lines and surrounding circuits are conveniently used.


PRIOR ART

Hot electron and tunnel current are used to extract electron from and to inject electrons into the floating gate of a floating gate type non-volatile memory device such as EEPROMS (electrically erasable programmable read only memories) and UVEPROMS (ultraviolet erasable programmable read only memories). Such a non-volatile memory device inherently requires a relatively long time to erase data therefrom and to write data therein as opposed to DRAMs and SRAMs,
Unless otherwise indicated, extraction of electrons from a floating gate refers to write operation and injection of electrons into a floating gate refers to erasure operation in the present invention.
Various methods of overcoming the above-mentioned drawbacks have been proposed. One such method is to provide a buffer memory based on SRAM and DRAM outside of a floating gate type non-volatile memory device. As shown in FIG. 10, This method makes it possible to temporarily storage of data from a CPU 20 into a buffer memory (RAM) 21 and to subsequently write the data into a floating gate type non-volatile semiconductor device (EEPROM) 22 at relatively slow speeds, thereby implementing shorter overall write time.
The write and erase operations of conventional floating gate type non-volatile memory devices are performed either in a method where hot electron is used to write data and tunnel current is used to erase the data, or in a method where tunnel current is used both to write and erase data. The former- method is typically used in so-called flash EEPROMs where data is erased at a time. The latter method is typically used in NAND type EEPROMs. A third method is used in UVEPROMs where hot electron is used to write data and ultraviolet rays are used to erase the data.
FIGS. 11A-11D illustrate distributions of threshold voltage of memory cells or transistors (referred to as memory transistor hereinafter) constituting the memory cells, plotting threshold voltage V.sub.TH as ordinate and frequency of occurrence of threshold voltage V.sub.TH as abscissa. FIGS. 11A-11D show flash type EEPROMs A and B, a NAND type EEPROM C, and a UVPROM D, respectively.
In the figures, logic "0" indicates a condition where a memory transistor's threshold voltage is high due to the accumulation of charge on the floating gate of the memory transistor so that little or no drain current flows through the memory transistor, i.e., data has been written hereinto. Logic "1" represents a condition where a memory transistor's threshold voltage is low due to the extraction of charge from the floating gate of the memory transistor so that some drain current flows or drain current is prone to flow, i.e., data has been erased therefrom.
As is clear from FIGS. 11A-11D, threshold voltages before write operation and after erasure operation, except the erasure of the UVEPROM, are widely distributed in any methods mentioned above. Hot electron and tunnel current are greatly affected by channel length, channel width, film thickness and uniformity of tunnel insulator film, drain voltage, and control gate voltage whose variations causes variations of threshold voltage of memory transistors.
Thus, the conventional semiconductor non-volatile memory devices need to be improved in terms of the distribution of threshold voltage in order to improve reliability of write and erase operations. One typical way of overcoming the deficiency is to provide a special logic circuit within the device to urge threshold voltages to converge within a desired range (K. N. Kynette et al., "An In-System Reprogrammable 32k.times.8 CMOS flash Memory, IEEE J. Solid-State Circuits," Vol. 23, No. 5 pp595-598, December 1992.) This method includes two

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